1. Field of the Invention
The present invention relates generally to data transfer circuits, and more particularly, to a data transfer circuit which transfers first and second data from a transmitting side circuit to a receiving side circuit.
2. Description of the Background Art
There are known conventional methods for internally transferring data in a semiconductor integrated circuit device, according to which a transmitting side circuit and a receiving side circuit are connected by a data line and voltage on the data line is changed by the transmitting side circuit for transferring data to the receiving side circuit. If data is thus transmitted by the voltage change on the single data line, however, noise affects the data line, which prevents the receiving side from determining the data to be received until voltage change equal to or greater than the level of the noise is obtained.
Therefore, in general, the transmitting side circuit and receiving side circuit are connected by two data lines provided in parallel, and the receiving side circuit is provided with a differential amplifier to amplify the potential difference between the data lines. According to this method, noise substantially equally affects the two data lines and the influence of the noise can be cancelled by taking the potential difference between the data lines. As a result, this method permits reception data to be determined with the voltage change between the data lines at a smaller level, faster data transfer than the data transfer method using the single data line can be achieved. This method however requires an equalizing operation before data transfer to bring the two data lines to the same potential level in order to compare the potentials of the two data lines.
FIG. 18 is a circuit block diagram of a conventional data transfer circuit using two data lines DL1 and DL2 and a sense amplifier SA, a kind of differential amplifier.
Referring to FIG. 18, in the data transfer circuit, the output nodes N201 and N202 of drivers 201 and 202 included in a data transmitting circuit TR and the input/output nodes N203 and N204 of sense amplifier SA included in the data receiving circuit are connected by data lines DL1 and DL2, respectively, and an equalizer EQ is provided between data lines DL1 and DL2.
Drivers 201 and 202 drive data lines DL1 and DL2 according to internal signals S1 and S2 based on transmission data, respectively. Equalizer EQ includes a P-channel MOS transistor 203 connected between data lines DL1 and DL2, and P-channel MOS transistors 204 and 205 connected in series between data lines DL1 and DL2. P-channel MOS transistors 203 to 205 receive together a data line equalize signal /DLEQ at their gates. Power supply potential Vdd is applied to the node between P-channel MOS transistors 204 and 205. When signal /DLEQ attains an xe2x80x9cLxe2x80x9d level, P-channel MOS transistors 203 to 205 conduct so that data lines DL1 and DL2 are equalized to power supply potential Vdd.
Sense amplifier SA includes P-channel MOS transistors 211 and 212 and N-channel MOS transistors 213 to 215 as shown in FIG. 19. P-channel MOS transistors 211 and 212 are connected between lines to power supply potential Vdd and input/output nodes N203 and N204, respectively, and have their gates connected to the input/output nodes N204 and N203, respectively. N-channel MOS transistors 213 and 214 are connected between input/output nodes N203 and N204 and node 205, respectively and have their gates connected to input/output nodes N204 and N203, respectively. N-channel MOS transistor 215 is connected between node N205 and a line to a ground potential Vss and receives a sense amplifier activation signal xcfx86SE at its gate. The potentials of input/output nodes N203 and N204 become output signals VO1 and VO2.
Sense amplifier SA is activated in response to sense amplifier activation signal xcfx86SE attaining an xe2x80x9cHxe2x80x9d level, and brings the node at the higher potential between input/output nodes N203 and N204 to power supply potential Vdd (xe2x80x9cHxe2x80x9dlevel) and brings the node at the lower potential to ground potential Vss (xe2x80x9cLxe2x80x9dlevel). Thus, the potential difference between input/output nodes N203 and N204 is amplified to power supply voltage Vdd.
FIGS. 20A to 20F are timing charts illustrating the operation of the data transfer circuit shown in FIGS. 18 and 19. Referring to FIGS. 20A to 20F, in an initial state, data line equalize signal /DLEQ is at an xe2x80x9cLxe2x80x9d level so that equalizer EQ is activated, and the potentials of data lines DL1 and DL2 are equalized to an xe2x80x9cHxe2x80x9d level. Sense amplifier activation signal xcfx86SE attains an xe2x80x9cLxe2x80x9d level and sense amplifier SA is inactivated. Internal signals S1 and S2 are both at an xe2x80x9cHxe2x80x9d level.
At time t0, data line equalize signal /DLEQ attains an xe2x80x9cHxe2x80x9d level, which turns off P-channel MOS transistors 203 to 205 in equalizer EQ, so that data transfer is enabled. Subsequently, at time t1, one of internal signals Si and S2 (S1 in the figure) attains an xe2x80x9cLxe2x80x9d level. Driver 201 attempts to pull data line DL1 to an xe2x80x9cLxe2x80x9d level, but the capacitance and resistance values of data line DL1 are large, and therefore the potential of data line DL1 gradually decreases.
At time t2, at which the potential difference between data lines DL1 and DL2 may be sensed and amplified by sense amplifier SA, sense amplifier activation signal xcfx86SE attains an xe2x80x9cHxe2x80x9d level, which turns on N-channel MOS transistor 215 in sense amplifier SA to activate sense amplifier SA. Thus, the potentials of data lines DL1 and DL2, in other words the output signals VO1 and VO1 of sense amplifier SA rapidly attain an xe2x80x9cLxe2x80x9d level and an xe2x80x9cHxe2x80x9d level, respectively, so that the data transfer ends.
After the data transfer, at time t3, signals /DLEQ and xcfx86SE are pulled to an xe2x80x9cLxe2x80x9d level and signals S1 and Sxe2x80x9d are pulled to an xe2x80x9cHxe2x80x9d level, thus equalizing data lines DL1 and DL2 to be ready for the next data transfer.
In the conventional data transfer circuit, however, after the equalizing operation is started at time t3, it takes a long period until the potentials of data lines DL1 and DL2 are completely pulled to the level of precharge potential Vdd, and during that period, the next data cannot be transmitted. If data lines DL1 and DL2 are long, the resistance and capacitance of the interconnections are large, and the time required for equalizing increases as a result. The interconnections are charged by equalizing, and therefore the power consumption increases if the data lines are longer.
It is therefore a main object of the present invention to provide a transfer circuit which permits the equalizing period and power consumption to be reduced.
Briefly stated, a transmitting circuit provides a potential difference between two data lines equalized to a first reference potential for transmitting first data and a potential difference to two data lines equalized to a second reference potential for transmitting second data. After the data transfer, a selecting circuit selects two data lines at potentials closer to the first reference potential as a first group and the other two data lines as a second group, and first and second equalizers equalize the first and second groups to the first and second reference potentials, respectively. The difference between the potential of a data line after the data transfer and the potential of the data line after the equalizing is smaller than the conventional case in which equalizing is performed regardless of the potentials of the data lines after the data transfer. Consequently, the equalizing period and power consumption can be reduced.
Preferably, the transmitting circuit pulls one of the two data lines equalized to the first reference potential to the second reference potential for transmitting the first data, and pulls one of the two data lines equalized to the second reference potential to the first reference potential for transmitting the second data. In this case, there is no potential difference between the potential of a data line after the data transfer and the potential of the data line after the equalizing, so that the equalizing period and power consumption can be even more reduced.
Also preferably, there are further provided a first amplifying circuit which amplifies a potential difference provided between the two data lines equalized to the first reference potential to pull one of the two data lines to the second reference potential and the other to the second reference potential and a second amplifying circuit which amplifies a potential difference provided between the two data lines equalized to the second reference potential to pull one of the two data lines to the first reference potential and the other to the second reference potential. In this case, since the difference between the potential of a data line after the data transfer and the data line after the equalizing is eliminated, the equalizing period and power consumption can be further reduced. The potential of the data lines can be changed at a high speed, and therefore the data transfer speed can be improved.
Also preferably, there are provided a first selecting circuit which selects one data line at the same potential as a predetermined data line, and a second selecting circuit which selects as a first group the predetermined data line if the data line is at the first reference potential together with the data line selected by the first selecting circuit and the other two data lines as a second group, and selects as a second group the predetermined data line if the data line is at the second reference potential together with the data line selected by the first selecting circuit and the other two data lines as a first group. Thus, the selecting circuit can be readily implemented.
Also preferably, the transmitting circuit includes first and second output nodes to transmit first data and third and fourth nodes to transmit second data, the receiving side circuit includes first and second input nodes to receive first data and third and fourth input nodes to receive second data, a first equalizer is coupled to the first and second input nodes, and a second equalizer is coupled to the third and fourth input nodes. A coupling circuit includes a first coupling circuit which couples respective one ends of the two data lines in the first group with the first and second output nodes, and respective one ends of the two data lines in the second group to the third and fourth output nodes, and a second coupling circuit which couples respective the other ends of the two data lines in the first group to the first and second input nodes, and respective the other ends of the two data lines in the second group to the third and fourth output nodes. Thus, the coupling circuit can be readily implemented.
Also preferably, the first coupling circuit includes a plurality of clocked inverters, and the second coupling circuit includes a plurality of transfer gates. In this case, the load of the transmitting circuit is alleviated by thus providing the clocked inverters.
The second coupling circuit includes first to fourth transfer gates provided corresponding the data lines and connected between the other ends of corresponding data lines and the first to fourth input nodes, respectively. The selecting circuit includes a storing circuit which stores information on which one of the first and fourth transfer gates conducts, and a control circuit which selects one of the first to fourth transfer gates based on the information stored by the storing circuit and the transferred first and second data. In this case, since the data lines and the receiving side circuit can be coupled by one stage of transfer gates, the load of the transmitting circuit can be alleviated.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.